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Instruction set architecture
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491	Introducing the EFM32 Wonder Gecko: An Energy Friendly MCU with Signal Processing Capabilities With the release of the EFM32 Wonder Gecko family, Energy Micro expands its MCU portfolio to combat energy consumption in mo Add to Reading List Source URL: www.silabs.com Language: English - Date: 2015-02-23 16:53:16 Microcontrollers ARM architecture Instruction set architectures Central processing unit Embedded microprocessors EFM32 Energy Micro ARM Cortex-M SIMD Computer architecture Computer hardware Computing
492	Microsoft Word - Cell PRESS RELEASE FINAL.doc Add to Reading List Source URL: www.scei.co.jp Language: English - Date: 2009-10-28 04:22:34 Semiconductor companies Microprocessors Instruction set architectures Power Architecture Digital electronics Cell IBM Multi-core processor Sony Electronic engineering Computer architecture Technology
493	Path-Exploration Lifting: Hi-Fi Tests for Lo-Fi Emulators Lorenzo Martignoni Stephen McCamant Pongsin Poosankam Add to Reading List Source URL: bitblaze.cs.berkeley.edu Language: English - Date: 2013-03-28 20:19:28 Programming language implementation Central processing unit Virtual machines Assembly languages Computer architecture Emulator QEMU Instruction set Bochs Software System software Computing
494	SH-5 Generic and C Specific ABI Language Independent Application Binary Interface The Language Independent ABI is intended to define the minimal conventions that must be used by all languages on the SH-5 architecture. T Add to Reading List Source URL: lars.nocrew.org Language: English Subroutines Assembly languages Instruction set architectures Microcontrollers X86 architecture Application binary interface Stack Addressing mode Function prologue Computing Software engineering Computer programming
495	TM SuperH (SH) 64-Bit RISC Series SH-5 CPU Core, Volume 3: Add to Reading List Source URL: lars.nocrew.org Language: English SuperH NOP Delay slot Computer architecture Instruction set architectures Microcontrollers
496	Part C Instruction scheduling Instruction scheduling character stream token stream Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2006-03-07 06:00:00 Central processing unit Compiler optimizations Hazard Instruction set Instruction scheduling CPU cache Cycles per instruction Instruction pipeline Computer architecture Computer hardware Computing
497	SH-5 Common Assembly Language Syntax Introduction The purpose of this document is to define a common assembly language subset to be followed by toolchains for the SH-5 architecture. Add to Reading List Source URL: lars.nocrew.org Language: English Assembly languages Computer engineering Instruction set architectures Programming language implementation SuperH Addressing mode Instruction set Operand IBM Basic assembly language Computer architecture Computing Machine code
498	TM SuperH (SH) 64-Bit RISC Series SH-5 CPU Core, Volume 4: Add to Reading List Source URL: lars.nocrew.org Language: English Computer hardware Microcontrollers SuperH Central processing unit Reduced instruction set computing Undefined behavior Processor register Comparison of CPU architectures Computer architecture Computing Instruction set architectures
499	SH-X3 Flexible SuperH Multi-core for High-performance and Low-power Embedded Systems 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:59:21 Cache coherency Instruction set architectures Embedded microprocessors Microcontrollers SuperH MESI protocol CPU cache Central processing unit Bus sniffing Computer hardware Computing Computer architecture
500	SH-MobileG1: A Single-Chip Application and Dual-mode Baseband Processor 1 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:56:34 Microcontrollers Embedded microprocessors SuperH Bus ARM architecture Interrupt request Computer architecture Instruction set architectures Computer hardware

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